Automated synthesis of asynchronous circuits using direct mapping for control and data paths

A method for automated synthesis of asynchronous circuits using direct mapping for control path and data path is presented. The idea of direct mapping is that a graph specification of a system is translated into a circuit netlist by mapping the graph nodes into circuit elements and the graph arcs into circuit interconnects. The key feature of this approach is its low algorithmic complexity and direct correspondence between the elements of the initial specification and the components of the resultant circuit. Unlike other direct mapping techniques, in our method the control path and data path are synthesised separately seeking for greater performance of the circuit. The control path synthesis starts from an initial specification in form of a Signal Transition Graph (STG). The STG is split into a device and an environment, which synchronise via a communication net that models wires. The device is represented as a tracker and a bouncer. The tracker follows the state of the environment and provides reference points to the device outputs. The bouncer interfaces to the environment and generates output events in response to the input events according to the state of the tracker. This two-level architecture provides an efficient interface to the environment and is convenient for subsequent mapping into a circuit netlist. A set of optimisation heuristics are developed to reduce the latency and size of the control circuit. The method for data path synthesis is based on a conventional RTL design flow. The data path components are first implemented by a standard RTL synthesis tool, e.g Synopsys. The obtained circuits are then converted into a hazard-free logic by using a dual-rail encoding with a return-tospacer signalling. A new protocol with two spacers alternating in time is proposed which makes all gates switch per computation cycle. The potential applications of this protocol are security circuits, online testing, dynamic logic. As a result of this work, several software tools are developed, namely OptiMist for synthesis of low-latency control path, and VeriMap for synthesis of hazard-free data path. The tools are successfully integrated in the BESST design flow to provide a front-end to high-level HDLs and an interface to conventional EDA tools for simulation, timing analysis and place-and-route.